Aquisition of Data triggered using a rising edge the Generated signal.

[Michael Collins]

I wish to set up the PXI-6551 to test an ADC.  It's a serial I/P ADC.  I've my board configured so that the data is fed out to a shift register. 
So I've an input digital stimulus which shifts out the data.  Then I wish to sample the ouput data on say the 19th clock edge in a looping fashion. 
Is this possible to assign a bit of my input digital stimulus as a trigger for acquisition.  At the moment I can set it up in a loop so that it begins
to sample at a certain point and will continuously sample thereafter on each clock edge.  This is not what I require.  So for example I've a
digital input stimulus of vector length 100.  This I will repetitively load to my ADC.  However it is only on the vector 100 which I wish to
sample the output.  Timing is very critical to this measurement.  So I don't wish to stop after each 100bit generation, take a reading, and
repeat the 100bit generation.  This must all happen at the speed of the internal clock.  Is this possible or has anyone any suggestions? 
 
Michael

[Michael Collins]

Hi Tom,
Thanks for your example.  I still have issue with my  implementation though. 
I've attached an ammended vi and doc showing the clocking required etc. 

Clock Rate = 20MHz

Trig Rate = 1MHz

Number of triggers = 1M.  (acquisition size = 1M samples)

 

In the figure below I?ve shown one period of the required digital pattern for writing and reading.  So for each 20 clocks written to the part, only one readback is performed.  The clock required is a continuous clock running at 20MHz.  Ideally this is internally generated by the 6552 I/O card. 

 

For smaller sample sizes (<8M), I could synchronously sample at each write and read at on each edge.  Then use readback offset properties etc to get the required data out.  This is however sampling 20 times the data required and will exceed the memory of the card. 

 

So my plan was to have control over the readback, by creating a ?Trig? signal as below and feed this back through PFI1 for example to sample the output.  The example you sent on is an attempt to do this is a round about way, however the speed of readback is limited using records etc.  I?ve amended this original example showing this, just by feeding an external clock source into PFI1.  Even is I increase this clock rate the records readback is sill limited to less that 1000 samples per second. 

 

Any further help much appreciated. 

 

Michael Collins

Analog Devices,

Limerick,

Ireland

 

353 61 494020
 


Acquisition Issue.doc:
http://forums.ni.com/attachments/ni/70/8364/1/Acquisition Issue.doc


Error Rate Test mc.vi:
http://forums.ni.com/attachments/ni/70/8364/2/Error Rate Test mc.vi