Hey AshishMaharjan,
Depending on which boards your channels are being used on, and depending on what rate you are running your clock at, you might be able to do this. I would recommend that you use the Data Delay feature of the 655x boards. With Data Delay, you can delay your data to a certain percentage from the clocks rising edge. Here is some information that can be found in the <a href="http://digital.ni.com/manuals.nsf/websearch/28328731D00E483786257361005589B4" target="_blank">NI Digital Waveform Generator/Analyzer Help</a> document:
"Data and Clock Position -- Your NI digital waveform generator/analyzer allows you to configure the subperiod time at which each waveform sample is generated or acquired. This subperiod time selection is referred to as the data position. You can also configure the position of the exported Sample clock (clock position). Configuring data and clock positions allows you to use your NI digital waveform generator analyzer for many common applications including, among others, measuring set-up and hold times, measuring propagation delays, and maximizing the timing margins among high-speed data transfers.
Delay from Sample clock rising edge?Data is generated/acquired at a specified time (specified in the niHSDIO Configure Data Position Delay VI or the niHSDIO_ConfigureDataPositionDelay function) after the rising edge of the clock driving the operation. The data position delay resolution depends on your clock frequency. Refer to the Acquisition and Generation books for your device for timing diagrams illustrating changing data position."
You can choose to generate your data on the Rising Edge of your clock, the Falling Edge of your clock, or at a Delay from the rising edge of the clock. This is settable for each channel, but you can only have one Delay value for each board for generation. So channel 0 can be rising edge, ch1 can be delay of 70%, ch2 can be falling edge, ch3 delay of 70%, ch4 rising edge, etc. etc. So if you need two delay values, then you need to have multiple boards. (You can also set up a delay value for all of your Acquisition channels as well, which can be different from your generation value) So if I understand your system setup correctly, you could have all three of your boards TClk'd together so their clocks are synchronized. Then you could have Signal A be off of the rising edge of board one, Signal B could be a Delay of 7 ns (at 100 MHz, which is 10 ns between clock pulses, you can choose a 70% delay from board one, and finally Signal C (13 ns) could be one clock cycle and a 30% from the rising edge. If you are running at 50 MHz (20 ns) then you can do a delay of (7/20)% and (13/20)%. Also, check out the following KnowledgeBase document called <a href="http://digital.ni.com/public.nsf/allkb/53BFD784329FF5BD86257210005D2004?OpenDocument" target="_blank">Handling HSDIO Data Delays Greater Than 100%</a>.
Now if I misunderstood what you are trying to do, then please clarify in more details. For example maybe you are trying to have a waveform that uses all 60 channels be generated for a certain number of samples, like 1000 samples. Then after waveform A is done generating all 1000 samples, you want to wait 7 ns and then generate waveform B for 100 samples. This is not possible to wait a subset of a sample between 2 waveforms. I don't think this is what you are trying to do, so Data Delay should work for you, but just for reference, I am letting you know about this use case. You can set the number of sample clocks to wait between two waveforms, but not a subset of a sample clock.
Check out the example programs called Dynamic Generation with Data Delay.VI and Round Trip Delay Elimination.VI. Hopefully these will help you add this functionality to your program. Let me know if you have any questions