jdviolin
2008-06-20 23:40:06 UTC
I am using a NI-6534 for Serial Digital Input. I am using the DAQmxCfgBurstHandshakingTimingImportClock() function in the same manner as in this post:
http://forums.ni.com/ni/board/message?board.id=70&thread.id=8334&view=by_date_ascending&page=1
That is, I'm using an "Enable" pulse to gate my data transmission. My
data transmission consists of a single, serial input data line and a
clock, on which the data is sampled (on the falling edge). The clock
is connected to PCLK and the Enable signal is connected to REQ signal.
Here is a diagram:
<img src="" style="padding: 7px 8px; background-color: #F6FEFF; border-left: 1px solid #8FF1FF; margin: 10px 0px; display: inline-block; color: #3B5053; font-size: 13px; ">Loading Image...![](https://natinst.public.daq.digital.general.narkive.com/muKCSnBY/handshake-adds-a-sample-at-the-beginning-and-omits-a-sample-at-the-end:i.1.1.thumb)
I am having trouble with the sampling. The first sample I get is
always '0', and I always miss the last sample of my data stream. Here
is a scope shot of the data (notice, it is viewed on the positive,
differential side, so ignore the voltages). Enable is on the bottom,
then data, then clock on the top. The data I sent out was 0x24.....
You can clearly see the '0 0 1 0 0 1 0 0' in the waveform, so I know
the data transmission hardware is working properly:
<img src="" style="padding: 7px 8px; background-color: #F6FEFF; border-left: 1px solid #8FF1FF; margin: 10px 0px; display: inline-block; color: #3B5053; font-size: 13px; ">Loading Image...![](https://natinst.public.daq.digital.general.narkive.com/muKCSnBY/handshake-adds-a-sample-at-the-beginning-and-omits-a-sample-at-the-end:i.1.2.thumb)
Any ideas? I will try to put up some pseudo-code Monday. Thanks for your assistance.
JOHN
http://forums.ni.com/ni/board/message?board.id=70&thread.id=8334&view=by_date_ascending&page=1
That is, I'm using an "Enable" pulse to gate my data transmission. My
data transmission consists of a single, serial input data line and a
clock, on which the data is sampled (on the falling edge). The clock
is connected to PCLK and the Enable signal is connected to REQ signal.
Here is a diagram:
<img src="" style="padding: 7px 8px; background-color: #F6FEFF; border-left: 1px solid #8FF1FF; margin: 10px 0px; display: inline-block; color: #3B5053; font-size: 13px; ">Loading Image...
I am having trouble with the sampling. The first sample I get is
always '0', and I always miss the last sample of my data stream. Here
is a scope shot of the data (notice, it is viewed on the positive,
differential side, so ignore the voltages). Enable is on the bottom,
then data, then clock on the top. The data I sent out was 0x24.....
You can clearly see the '0 0 1 0 0 1 0 0' in the waveform, so I know
the data transmission hardware is working properly:
<img src="" style="padding: 7px 8px; background-color: #F6FEFF; border-left: 1px solid #8FF1FF; margin: 10px 0px; display: inline-block; color: #3B5053; font-size: 13px; ">Loading Image...
Any ideas? I will try to put up some pseudo-code Monday. Thanks for your assistance.
JOHN