ztruth
2006-10-20 14:40:13 UTC
Hi All
System Specs:
I am using a 6602 pci card (R6868 cable to TBX68).
I have LV8.2 code to output (4) 1KHz counter outputs (3) of which are delayed by 1us.
I use Same Trigger for all (4) continuous counters from io port0 line0 to PFI38.
Issues:
The 5V TTL high level of the 1st counter exhibits a 1V dip during the rise time of the other 3 delayed counters.
Support requested:
1. How to; filter the voltage dipping affect ?
2. How to; decrease the rise time [currently100ns].
Thanks
Ryan
System Specs:
I am using a 6602 pci card (R6868 cable to TBX68).
I have LV8.2 code to output (4) 1KHz counter outputs (3) of which are delayed by 1us.
I use Same Trigger for all (4) continuous counters from io port0 line0 to PFI38.
Issues:
The 5V TTL high level of the 1st counter exhibits a 1V dip during the rise time of the other 3 delayed counters.
Support requested:
1. How to; filter the voltage dipping affect ?
2. How to; decrease the rise time [currently100ns].
Thanks
Ryan