Interfacing with a JTAG state machine on a FPGA using the USB-6229 device

[K C]

Hi Michael,
 
One of the benefits of Jtag is that it is a simple hardware interface. Most of the time you don't need the reset so the only thing left is a mode (TMS), clock (TCK) and data signals (TDI and TDO)
I think you can find the detailed information on internet if not tell me I will dig into my books and papers.
 
You didn't mentioned if you want to program this in LV or ?

[K C]

Hi Michael,
 
I don't think you can find anything that you can use directly.
 
Making a program is not a problem, finding the time that is a problem  :smileywink:
 
How much time do you have before is has to be ready ?.
 
How much data you want to handle ? Programming a big FPGA can take a lot of time because in this way you have to program every change of a digital line and your USB device is limited to 1MHz.

[K C]

Hi,
 
I hope I didn't scare you of  :smileysurprised:
 
Where are you located ?
 
Greetings from The Netherlands

[K C]

Hi Michael,
Are you still working on your Jtag interface in LV ?

[K C]

Yes, Jtag technologies and there are more suppliers with Jtag boards.
I don't exactly know if you can buy a controller with LV support without the software for Jtag test. The software is very expensive, but the last time I was involved in buying this was over 10 years ago. So I am not up-to-date about what is on the market.