PXI-6552 intermittently fails when external sampling clock is changed

[Flieger]

I am using PXI-6552 HSDIO and a PXI-5404 (Signal generator) in PXI-1036 chassis with LabView 8.0.
To use fractural sampling frequency (e.g. 88.1MHz), I use external sampling clock that is generated by 5404 in slot 2 and given through PXI STAR lines to 6552.
It works fine when I use fixed sampling frequency,  But when I start changing it, 6552 sometimes failed to work (>1%).I got Hardware clocking error. (Error -1074115898 occurred at niHSDIO Initiate.vi)
In my program, Frequency change and niHSDIO Initiate are in While Loop.
Using CLKIN port did not solve this problem.  But I do not see this problem when I use on-board clock.
The sampling frequency where such failure occur are in certain ranges, for example, around 55MHz and 95MHz.I have another 6552 in different slot which also fails similarly but at  slightly different frequencies.
I tried to put Time Delay here and there but it did not help me.
Does anybody have idea how can I solve it?
 
HSDIO version is 1.4.2.4.
 

[Nick Storton]

Hi Flieger,
I'm guessing that the problem you are seeing here is that you are setting the HSDIO to work initially with a sample clock frequency equal to the initial clock frequency of the 5404 (88.1 MHz) you are then generating continuously from the HSDIO and changing the 5404 clock rate over time. The HSDIO then phase locks it's internal OCXO to this external clock to run the board. If the external clock frequency changes and goes outside of the lock range of the PLL the driver will throw an error which is what you are seeing. You will need to re-program the HSDIO sample rate to match the new clock rate as you change the clock from the 5404, although you can use the lock range so that you don't need to continuously change the HSDIO.
Hope this helps,
Nick

[Flieger]

Hi Nick,
 
Thank you for your suggestion.
However I have already used Configure Sample Clock in my program to set new sampling frequency.
 
I added niFgen Abort Generation before setting new frequency to 5404 to allow HSDIO to leave locked frequency bit earlier but situation did not change.


freq_setup.JPG:
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freq_setup2.JPG:
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[Ryan M]

Hi Flieger,

Nick is correct.  When you call HSDIO Initiate, the NI-HSDIO
driver will setup the on board DLL's to work properly at the frequency
you input using the Configure Sample Clock VI.  Once the DLL's
locked, there is a small range over which the frequency may drift but
it is not guaranteed and may not be deterministic.  Instead, to
guarantee that the clocking will work, every time you change the
frequency of the input clock, you should stop the generation, change
the frequency using the Configure Sample Clock VI, and reinitiate the
task.  In this fashion, the driver will attempt to relock the
clocks to the frequency source.

Thanks, Ryan

[Flieger]

I created VI to reproduce this problem.Three frequency changing method were tried.  Sequencial, random and hopping two predefined frequencies.Here is the result In my case.

- Sequencial: Almost no error, but not error free.

- Random: about 1%

- Hopping two freq.:  20-25%


Freq change2.vi:
http://forums.ni.com/attachments/ni/70/5453/1/Freq change2.vi

[Nick Storton]

Hi Flieger,
I have run this vi on my system and can confirm that I see the same error that you describe. I have tried quite a number of different things to try and resolve the issue with no luck. Some of the things reduce the error rate but nothing so far has fixed the issue. I think this is something that requires your local NI branch to investigate further and maybe to escalate the issue to NI R&D. Sorry I can't be any more help but this seems to be something a bit more fundamental than can be fixed by different programming methods.
Nick

[Flieger]

Hi Nick,
it seems that this needs help from NI.   I will make a contact with them.I appreciate your taking time to investigate my problem.
Thank you.