Multiple Delay on the same HSDIO PXI-6552 card

[noname0]

Hi,
I m trying to assign different delay on different channel. Let say, Channel1 delay by 5ns, Channel2 delay by 10ns..
From the help file, it state that the delay must be the same, and I have try different delay value and it cause an error.

"delay specifies the delay after the Sample clock rising edge when the device generates or acquires a new data sample. Data delay is expressed as a fraction of the clock period. "
"All the channels in the session that use delayed sample clock to position data must have the same delay value. "
 
Does anyone here have alternative way to solve this ? Thanks..

[Jaime F]

Hi,


I first want to clarify if I understand what you are asking,
you are talking about: Delay from sample clock rising edge as stated in the
HSDIO help like: ?The device samples or generates data with a delay from the
Sample clock rising edge. Specify the delay using the Data Position Delay
property. This choice has more jitter than the rising or falling edge values.
Certain devices have Sample clock frequency limitations on when a custom delay
can be used. Refer to the device documentation for details?.


You can see we sate that for the delay on NI 656x devices,
you must delay all channels on the device or NI-HSDIO will returns an error if
you apply a delay to only a partial channel list.


Some useful examples I have found are: <a href="http://digital.ni.com/public.nsf/allkb/53BFD784329FF5BD86257210005D2004" target="_blank">Handling
HSDIO Data Delays Greater Than 100%</a>, <a href="http://zone.ni.com/devzone/cda/epd/p/id/5313" target="_blank">Proof of Concept:
Synchronized HSDIO Generation with Data Delay</a>, <a href="http://zone.ni.com/devzone/cda/epd/p/id/5227" target="_blank">HSDIO: Dynamic Acquisition
Multiple Data Delay</a>.


Ok enough of theory and let?s get back to your problem, I
did run an example similar to yours and I do get the same error message. I?m
sorry to inform that in the same way we only support voltage levels in a per
device devices basis like:&nbsp; <a href="message?board.id=70&amp;message.id=8920&amp;requireLogin=False" target="_blank">Different
voltage for HSDIO Channel</a>


Solution: &nbsp;if your concern is propagation delay, making
all the cables the same should fix the problem in the case one channel cable length
is different from the other. Other option is to post process the data and drop
the unwanted data from channel&nbsp; 2.


I hope it helps

[noname0]

Thanks for your reply.
Ya, this is what I'm asking about. I m having this problem due to&nbsp;the conditions that :

- Channel0 = Dynamic Generation without delay (rising clock)

- Channel1 = with delay 5ns

- Channel2 = with delay 10ns

From the help file, I hv found that in the same generation session, the data delay value must be the same. Maybe 2 HSDIO card will do it, but I m still seeking the possible solution by using the same HSDIO card.

[Ryan M]

noname, the 655x only supports a single delay value applied to the "delayed from rising edge" data position.&nbsp; This delay gets applied to all channels that select that data position mode.&nbsp; On a per channel basis you can select if you want a channel to be generated on the "rising edge", "falling edge", or "delayed from the rising edge", but you can only apply a single delay value per board.&nbsp; However, for your particular application, you require delays of 0ns, 5ns, and 10ns.&nbsp; These values map exactly to a 100MHz clock rate generating data on the rising edge (0ns delay), falling edge (5ns), and a rising edge with a single sample delay (10ns).&nbsp; To achieve the sample delay, you would need to use your software code to delay that particular data bit by a sample.For example, if your waveform was000111000111000...Your software would write this waveform to memory00x110001110001xx0...Since your clock rate is 100MHz, the sample delay would appear like a 10ns delay.&nbsp; Does that make sense?Additionally, for the sake of completeness, the 655x also supports an exported clock delay that is independent of the data delay.&nbsp; That is, you can delay your data from the sample clock by a some percentage, and you can export your clock from the sample clock by some other percentage.&nbsp; If you application only required the 5ns and 10ns delays then you could delay your clock by some percentage of your period to give you 5ns on rising edge, then your data by an additional percentage to get you to 10ns.

[noname0]

Thanks for giving me such a wonderful idea .. :) Thanks again ..

[DJ L.]

Hey noname0,
You have seen some great ideas. I just wanted to throw one more out there for ya. Since you have not mentioned anywhere in your posts at what rate you want to run, but just that you want the rising edge, a 5 ns delay and a 10 ns delay. Also because the 6552 can run at rates up to 100 MHz, I thought of another option you might be able to use, especially if you only need those three times to generate (or acquire) data. Instead of running your clock at 100 MHz which gives you a 10 ns period, you can run at 50 MHz, which will give you a 20 ns period. Then your 3 channels would look like this:

- Channel0 = Dynamic Generation without delay (Rising Edge of the clock = 0 ns)

- Channel1 = Delay of 25%&nbsp;(25% of 20 ns = 5ns)
- Channel2 = Falling Edge of the&nbsp;clock (half of&nbsp;20 ns&nbsp;= 10 ns)

Hope this helps.
Regards,DJ L.

[noname0]

Wow .. it seems would work too .. I will try it .. Really Thanks to you guys !!