jrjones
2006-06-12 19:40:11 UTC
I am using LabVIEW 7.1.1 and a DIO-32HS w/ SCB-68 (connection reference label P/N 185754B-01). I am trying to communicate with the Serial Control Interface of a custom ASIC. I need to generate an internal clock for the data in & out of the chip (see attached timing diagram). I have much LabVIEW experience, but am not a frequent user of I/O cards or DAQmx. I'm unable to produce the desired results and the problems are related to having the external clock for the output available at the SCB terminals while also used as the clock for the input.
The attached VIs are two versions of the same basic code with slightly different setups.
The HW setup for ASIC SCI_2.vi only has a connection between P0.2 & P2.0 to loopback a signal for testing the code.
The HW setup for ASIC SCI_3.vi adds another connection between PFI 4 and PFI 5 intended to loopback the clock.
Thanks for any suggestions on how to correct my problem.
James
PS. To run the VI, just delete the case with the missing VI, there is default data in the false case.
ASIC SCI_3.vi:
http://forums.ni.com/attachments/ni/70/5034/1/ASIC SCI_3.vi
ASIC SCI Timing.jpg:
http://forums.ni.com/attachments/ni/70/5034/2/ASIC SCI Timing.jpg
ASIC SCI_2.vi:
http://forums.ni.com/attachments/ni/70/5034/3/ASIC SCI_2.vi
The attached VIs are two versions of the same basic code with slightly different setups.
The HW setup for ASIC SCI_2.vi only has a connection between P0.2 & P2.0 to loopback a signal for testing the code.
The HW setup for ASIC SCI_3.vi adds another connection between PFI 4 and PFI 5 intended to loopback the clock.
Thanks for any suggestions on how to correct my problem.
James
PS. To run the VI, just delete the case with the missing VI, there is default data in the false case.
ASIC SCI_3.vi:
http://forums.ni.com/attachments/ni/70/5034/1/ASIC SCI_3.vi
ASIC SCI Timing.jpg:
http://forums.ni.com/attachments/ni/70/5034/2/ASIC SCI Timing.jpg
ASIC SCI_2.vi:
http://forums.ni.com/attachments/ni/70/5034/3/ASIC SCI_2.vi