NI_Inept
2007-08-06 22:40:16 UTC
Using a 6534 DIO. I created a VI that sets up port 0:1 to read with a hardware trigger on PFI6, and then in the same vi I write to port 2:3, which I hardwired one of the bits on that port to PFI6, in effect creating a self-triggering sequence. This works most of the time but I'm guessing that since the two processes aren't synchronized, the "write trigger" may happen before the read becomes initialized and is waiting for the trigger. I inserted a sequence with a time delay and that works, but it would be better if I could somehow synchronize these two processes. During my experimentation I can't determine when the triggered read is really ready. Common sense tells me it's ready after the DAQmx Start/Rising edge vi, but it only seems to work once the DAQmx Read/1D Wfm/1sample vi gets called. Ideally there'd be some kind of "trigger ready" VI I could use to initiate the write trigger sequence instead of waiting some arbitrary amount of time. I experimented a bit with the DAQmx Is Task Done but I still can't prove exactly when the read is configured *and ready* for a trigger. The fact that it works at all tells me this should be possible, and more time efficient if I could properly sequence the trigger after the "read ready". Can anyone tell me how I can synchronize this read/write timing? Thanks. (Deficient Code Attached)
Mark B.
Albuquerque, NM
SelfTrigDIO_DataRead.vi:
http://forums.ni.com/attachments/ni/70/7288/1/SelfTrigDIO_DataRead.vi
Mark B.
Albuquerque, NM
SelfTrigDIO_DataRead.vi:
http://forums.ni.com/attachments/ni/70/7288/1/SelfTrigDIO_DataRead.vi