fast data acq. with 6601

[BZajec]

I intend to use the PCI-6601 for the following task:

 

We have a fast ADC (13 bit) that has:

13 digital outputs for bit0...bit12 and

data ready (DR)   (all TTL)

 

The digital input (TTL) to this ADC is  data accepted (DA) that tells ADC when the digital lines have been read and it can put new number on the output.

 

I would like to use 6601 to read those 13 digital lines from ADC when DR makes low-->high transition, i.e. I will use the triggered data acquisition. After each digital pattern has been read I need also to send a TTL pulse back to ?data accepted? input line on ADC.

 

In addition to this, I also need to count the TTL pulses coming from digital-to-current-integrator, their frequency is max. 10kHz.

 

The program in LabView will act as a MultiChannel Analyzer (MCA) for values coming from ADC. The histogram should be refreshed at least twice per second. The number of counts from the digital-to-current-integrator should also to be displayed with the approximately same rate.

 

I believe the 6601 is the right card for this job.

 

My question is: what is the highest frequency of values from the ADC that the 6601 will be able to collect without losses and in continuous operation?

 

regards,

 

Bojan

 

[Robert F]

Hello Bojan,




Do you already have a PCI-6601 or are you looking for a
solution?




The NI-6601 DI/O is only software timed.  This means that there is no reliable value
that I can provide identifying how many times this process can be
repeated.  However, you could do
everything in software.  Have a program
that acquires digital data within a loop as fast as possible, that monitors the
Data Ready pin.   The comparison needs to
be done in software.  Once you detect a
rising edge or logic change, read in the digital data from the ADC.  After that call has been executed, send a
digital pulse on the Data Accepted pin. 
As you can guess, this method is not the best way to monitor your ADC.
Find the right DAQ board <a href="http://www.ni.com/dataacquisition/" target="_blank">here</a>.




I would suggest a M-Series board (62xx) for a solution that
has hardware timed DI/O. &nbsp;With this
solution the DR pin can monitored for change detection which would latch the
digital data without interfacing with the software.&nbsp; The rising edge of the DR pin can trigger a
retriggerable finite pulse train of one pulse.&nbsp;
This pulse train could be generated with a slight delay which would make
sure that the data was latched in correctly.&nbsp;
This delay will depend on your device (ADC) but is probably very small
if it exists at all.&nbsp;




If you decide to go with an M-Series board (62xx), then both
of the counters will be used for the finite retriggerable pulse train.&nbsp; This means that you might need a counter
board to count the frequency of the digital-to-current integrator.&nbsp;

[BZajec]

Dear Rob,
&nbsp;
&nbsp;Thank you very much for your answer.
&nbsp;
&nbsp;I do not have the 6601, I wanted first find out if it is the right card for this job.






The NI-6601 DI/O is only software timed.&nbsp; This means that there is no reliable value that I can provide identifying how many times this process can be repeated.&nbsp; However, you could do everything in software.&nbsp; Have a program that acquires digital data within a loop as fast as possible, that monitors the Data Ready pin.&nbsp;&nbsp; The comparison needs to be done in software.&nbsp; Once you detect a rising edge or logic change, read in the digital data from the ADC.&nbsp; After that call has been executed, send a digital pulse on the Data Accepted pin.&nbsp; As you can guess, this method is not the best way to monitor your ADC.


So you are saying it is not possible to trigger the read of digital inputs directly to the change state of DR?&nbsp;&nbsp; You want to say that triggering at 6601 refers only to counters, but not to ordinary DIO lines?
&nbsp;
&nbsp;
&nbsp; I would then go with PCI-6220 (M series), but I run out of counters as you noted.&nbsp;&nbsp;&nbsp;Is it perhaps possible to create a triggered and&nbsp;short &nbsp;(few microsec.) TTL pulse using the analog output (if I use PCI-6221)?&nbsp; This would save the 2nd counter for the pulses from current-integrator.
&nbsp;
&nbsp;&nbsp;&nbsp;Is with&nbsp;PCI-6221 (or 6220)&nbsp; then possible to read and do the MCA (as described in previous post) with the ADC conversion frequency up to 800kHz ?
&nbsp;
&nbsp;
regards,
&nbsp;
&nbsp;Bojan Z.
&nbsp;&nbsp;

[Robert F]

Hello Bojan,




You could create an analog output waveform that simulates a
digital pulse if you select the PCI-6221.&nbsp;
The problem with using an analog output is trying to generate a clock to
output the samples that is retriggerable. Normally, you would use two counters
to create a finite retriggerable pulse train that can be used as the sample
clock.&nbsp; So using the analog output does
not solve your problem of freeing up a counter.




The best solution might be to use a PCI-6220 or PCI-6221
with a counter/timer board.&nbsp; This will
allow you to interface correctly with the ADC.&nbsp;
PCI boards can be synchronized if a RTSI cable is used. &nbsp;&nbsp;

Message Edited by Robert F on 12-18-2007 12:09 PM

[BZajec]

Dear Robert,

&nbsp;

&nbsp;I bought PCI-6221 some months ago. Then I was busy with other things and now I am back working on this data acquisition matter.

&nbsp;

&nbsp;Currently I am only interested how to read the 13 digital lines when the Data Ready line from ADC goes high and how to send the Data Accepted back after the 13 digital lines have been read. No need to take care of the other TTL signal that would require additional counter.

&nbsp;

After trying to put this together and having problems in LabView I went back searching the discussion forum and found the following:

&nbsp;

The M-series 6221 has ONLY port 0 (8 DIO lines) hardware timed, all other DIO lines cannot be hardware timed.

&nbsp;

Is there any way that I can have HW triggered read-in of 13 digital lines with PCI-6221 ? (two consecutive trigger signals (Data Ready) can be only few microseconds apart)

&nbsp;

Would it be possible to use 5 analog input lines to have HW triggered read-in of the remaining 5 digital lines ?

How is the buffering then?

&nbsp;

&nbsp;

I would like to have the 13 digital lines read-in in less than few (max. 10) microseconds.

&nbsp;

Or is the e.g. M-series 6224 with port 0 of 32 DIO lines the only possible solution?







&nbsp;

I am looking forward to hear from you soon.

&nbsp;

with best regards,

&nbsp;

Bojan

&nbsp;