cig438
2006-10-24 16:10:11 UTC
I have a 6514 card & am trying to create 2 pulse trains one delayed
w.r.t the other by half the pulse width. I can get it to delay by a
full pulse width. My pulse widths are 100ms. Attached is a picture of
what I can achieve. I'm using timed sequences & delaying the SCLOCK
by 150ms w.r.t. SDATA. I'm currently ignoring the SLOAD line. Attached
is the vi.
I realize that the best way to implement this would be to use a board
that is capable of hardware timing, but at this point I'm trying to
work around thru software. Because of my software timing, any timing
less than ~ 50ms is unreliable (unless I'm underestimating the power of
the controlled timing vi's ?).
How can I implement this 50ms stagger between SDATA & SCLOCK ?
Any suggestions would be greatly appreciated.
Thanks,
ak
phased pulse trains.xls:
http://forums.ni.com/attachments/ni/70/5689/1/phased pulse trains.xls
pulse trains.vi:
http://forums.ni.com/attachments/ni/70/5689/2/pulse trains.vi
w.r.t the other by half the pulse width. I can get it to delay by a
full pulse width. My pulse widths are 100ms. Attached is a picture of
what I can achieve. I'm using timed sequences & delaying the SCLOCK
by 150ms w.r.t. SDATA. I'm currently ignoring the SLOAD line. Attached
is the vi.
I realize that the best way to implement this would be to use a board
that is capable of hardware timing, but at this point I'm trying to
work around thru software. Because of my software timing, any timing
less than ~ 50ms is unreliable (unless I'm underestimating the power of
the controlled timing vi's ?).
How can I implement this 50ms stagger between SDATA & SCLOCK ?
Any suggestions would be greatly appreciated.
Thanks,
ak
phased pulse trains.xls:
http://forums.ni.com/attachments/ni/70/5689/1/phased pulse trains.xls
pulse trains.vi:
http://forums.ni.com/attachments/ni/70/5689/2/pulse trains.vi