How to synchronize and/or divide sample clock for PXI-6551

[scrib]

We're using a PXI-6551 (HS-DIO module) and need to be able to either synchronize the on-board sample clock to an external periodic signal,
or we need to derive a lower frequency sample clock from the CLK_IN input (divided down) synchronized to an external periodic signal.
Is any of this feasible? How?
 
 
Thanks in advance,
joe

[Matt A]

Hello Joe,The ability to "synchronize" your on board sample clock to an external clock will depend on the frequency of the external clock. I have copied the block diagram for the clocking circuitry on the NI 6551 below. This diagram is in the section entitled "Clocking" in the NI 655x section of the <a href="http://digital.ni.com/manuals.nsf/websearch/28328731D00E483786257361005589B4" target="_blank">NI Digital Waveform Generator/Analyzer Help</a>. As you can see, there is no clock divider circuitry on the NI 6551 that directly divide down an external clock, only the clock divider for the internal clock highlighted in the figure. However, rather than dividing down the external clock on board, you can PLL the on board clock to a 10 MHz Reference Clock and that will ensure that your sample clock is phase synchronized to your external clock. However, as shown on page 17 of the <a href="http://www.ni.com/pdf/manuals/373309d.pdf" target="_blank">NI PXI/PCI-6551/6552 Specifications</a>, the external reference clock must be almost exactly 10 MHz (I have copied this information for your reference below. Another important factor about the reference clock is that it is limited to terminals that can accept a higher bandwidth (10 MHz) signal. Again, this issue is addressed in the NI Digital Waveform Generator/Analyzer Help in the section "Clock Sources Summary" under the NI 655x section, which I have copied below.I hope this information addresses your question, feel free to post back if you have any other questions.


NI 6551 Reference Clock Sources.png:
http://forums.ni.com/attachments/ni/70/8116/1/NI 6551 Reference Clock Sources.png


NI 6551 Clocking.png:
http://forums.ni.com/attachments/ni/70/8116/2/NI 6551 Clocking.png


NI 6551 Reference Clock.png:
http://forums.ni.com/attachments/ni/70/8116/3/NI 6551 Reference Clock.png

[Matt A]

Hello Joe, I apologize for my mistake but I was not able to copy the images in-line with the text. Here is my original post with images placed appropriately:" Hello Joe,The ability to "synchronize"
your on board sample clock to an external clock will depend on the
frequency of the external clock. I have copied the block diagram for
the clocking circuitry on the NI 6551 below. This diagram is in the
section entitled "Clocking" in the NI 655x section of the <a href="http://digital.ni.com/manuals.nsf/websearch/28328731D00E483786257361005589B4" target="_blank">NI Digital Waveform Generator/Analyzer Help</a>.
As you can see, there is no clock divider circuitry on the NI 6551 that
directly divide down an external clock, only the clock divider for the
internal clock highlighted in the figure. <img src="Loading Image..."> However,
rather than dividing down the external clock on board, you can PLL the
on board clock to a 10 MHz Reference Clock and that will ensure that
your sample clock is phase synchronized to your external clock.
However, as shown on page 17 of the <a href="http://www.ni.com/pdf/manuals/373309d.pdf" target="_blank">NI PXI/PCI-6551/6552 Specifications</a>, the external reference clock must be almost exactly 10 MHz (I have copied this information for your reference below. <img src="Loading Image..."> Another
important factor about the reference clock is that it is limited to
terminals that can accept a higher bandwidth (10 MHz) signal. Again,
this issue is addressed in the NI Digital Waveform Generator/Analyzer
Help in the section "Clock Sources Summary" under the NI 655x section, which I have copied below.<img src="Loading Image..."> I hope this information addresses your question, feel free to post back if you have any other questions.
"

[scrib]

Matt,
Thanks so much for the response. Unfortunately, I was not crystal clear with my original post.
Given that I'm able&nbsp;to programmatically&nbsp;divide down the&nbsp;on-board clock, can I have the divide-down initiate at a&nbsp;trigger edge (this is the synchronous external signal I was referring to in my original post that I erroneously described as periodic -- it is not periodic -- it is a one-shot trigger edge)?
It appears I'm not able to capture samples consistently starting at&nbsp;a trigger edge because the on-board divided-down clock is not synchonous with the trigger edge.
I'm assuming this is because the on-board clock does not initiate the divide-down based on anything I have control over.&nbsp; Is there a feature that allows me to initiate the divide-down of the on-board clock with an external trigger edge?
Thanks,
Joe

[Jaime F]

Hi,

The clock is always going to start when the trigger is received. &nbsp;Depending on the trigger mode you select you will have different behaviors in your case you are looking to do: "digital edge", the data operation does not start until a digital edge is detected. ?Digital Edge: the source of the digital edge is specified with the Digital Edge Start Trigger Source property, and the active edge is specified with the Digital Edge Start Trigger Edge property.?&nbsp;&nbsp;

Make sure you are setting up number of samples to be acquired per record and total number of records you want to acquire correctly. Now the question would be how fast is your trigger? What are the voltage levels for the trigger? Check that everything is under specifications page 20 of <a href="http://arapaho-app.natinst.com:8000/pls/nic3/niae_screenpop.main?p_incident_number=1106947http://www.ni.com/pdf/manuals/373309d.pdf" target="_blank"> 6551 Manuals</a> .

I hope it helps